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1/21 not for new design june 2004 this is information on a product still in production but not recommended for new designs. m24m01 1 mbit serial i2c bus eeprom features summary 400khz high speed two wire i 2 c serial interface single supply voltage: ? 2.7v to 3.6v for m24m01-v ? 1.8v to 3.6v for m24m01-s write control input byte and page write (up to 128 bytes) random and sequential read modes self-timed programming cycle automatic address incrementing enhanced esd/latch-up behavior more than 100000 erase/write cycles more than 40 year data retention figure 1. packages lga8 (la) lga
m24m01 2/21 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. lga connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 power on reset: vcc lock-out write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 chip enable (e1, e2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 write control (wc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. maximum rl value versus bus capacitance (cbus) for an i2c bus . . . . . . . . . . . . . . . . 5 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 start condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. device select code 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. i2c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. write mode sequences with wc=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 8 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 byte write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. write mode sequences with wc=0 (data write enabled). . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 8. write cycle polling flowchart using ack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 minimizing system delays by polling on ack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 9. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 sequential read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3/21 m24m01 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 initial delivery state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. operating conditions (m24m01-v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. operating conditions (m24m01-s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. power-up timing and vth threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10. dc characteristics (m24m01-v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11. dc characteristics (m24m01-s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 12. ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. lga8 - 8 lead land grid array, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 13. lga8 - 8 lead land grid array, package mechanical data . . . . . . . . . . . . . . . . . . . . . . 18 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 14. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 15. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
m24m01 4/21 summary description the m24m01 is a 1 mbit (131,072 x 8) electrically erasable programmable memory (eeprom) ac- cessed by an i 2 c-compatible bus. figure 2. logic diagram table 1. signal names i 2 c uses a two wire serial interface, comprising a bi-directional data line and a clock line. the devic- es carry a built-in 4-bit device type identifier code (1010) in accordance with the i 2 c bus definition. the device behaves as a slave in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiat- ed by a start condition, generated by the bus mas- ter. the start condition is followed by a device select code and rw bit (as described in table 2), terminated by an acknowledge bit. when writing data to the memory, the device in- serts an acknowledge bit during the 9 th bit time, following the bus master?s 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and after a noack for read. figure 3. lga connections note: 1. du = don?t use (should be left unconnected, or tied to v ss ) power on reset: v cc lock-out write protect in order to prevent data corruption and inadvertent write operations during power-up, a power on reset (por) circuit is included. at power-up, the internal reset is held active until v cc has reached the por threshold value, and all operations are disabled ? the device will not respond to any com- mand. in the same way, when v cc drops from the operating voltage, below the por threshold value, all operations are disabled and the device will not respond to any command. a stable and valid v cc must be applied before applying any logic signal. when the power supply is turned on, v cc rises from v ss to v cc (min), passing through a value v th in between. the device ignores all instructions un- til a time delay of t pu has elapsed after the mo- ment that v cc rises above the v th threshold. however, the correct operation of the device is not guaranteed if, by this time, v cc is still below v cc (min).no instructions should be sent until the later of: ?t pu after v cc passed the v th threshold ?v cc passed the v cc (min) level these values are specified in table 9. e1, e2 chip enable sda serial data scl serial clock wc write control v cc supply voltage v ss ground ai04048b sda v cc m24m01 wc scl v ss 2 e1-e2 sda v ss scl wc e1 du v cc e2 ai04051c m24m01 1 2 3 4 8 7 6 5
5/21 m24m01 signal description serial clock (scl). this input signal is used to strobe all data in and out of the device. in applica- tions where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from serial clock (scl) to v cc . (figure 4 indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of synchro- nization is not employed, and so the pull-up resis- tor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. serial data (sda). this bi-directional signal is used to transfer data in or out of the device. it is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull up resistor must be connected from se- rial data (sda) to v cc . (figure 4 indicates how the value of the pull-up resistor can be calculated). chip enable (e1, e2). these input signals are used to set the value that is to be looked for on bits b3 and b2 of the 7-bit device select code. these inputs must be tied to v cc or v ss , to establish the device select code. when unconnected, the chip enable (e1, e2) signals are internally read as v il (see table 10 and table 11). write control (wc ). this input signal is useful for protecting the entire contents of the memory from inadvertent write operations. write opera- tions are disabled to the entire memory array when write control (wc ) is driven high. when uncon- nected, the signal is internally read as v il , and write operations are allowed. when write control (wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. figure 4. maximum r l value versus bus capacitance (c bus ) for an i 2 c bus ai01665 v cc c bus sda r l master r l scl c bus 100 0 4 8 12 16 20 c bus (pf) maximum rp value (k ? ) 10 1000 fc = 400khz fc = 100khz
m24m01 6/21 device operation the device supports the i 2 c protocol. this is sum- marized in figure 2. any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. the m24m01 device is always a slave in all communication. start condition start is identified by a falling edge of serial data (sda) while serial clock (scl) is stable in the high state. a start condition must precede any data transfer command. the device continuously monitors (except during a write cycle) serial data (sda) and serial clock (scl) for a start condition, and will not re spond unless one is given. stop condition stop is identified by a rising edge of serial data (sda) while serial clock (scl) is stable and driv- en high. a stop condition terminates communica- tion between the device and the bus master. a read command that is followed by noack can be followed by a stop condition to force the device into the stand-by mode. a stop condition at the end of a write command triggers the internal ee- prom write cycle. acknowledge bit (ack) the acknowledge bit is used to indicate a success- ful byte transfer. the bus transmitter, whether it be bus master or slave device, releases serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits. data input during data input, the device samples serial data (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driv- en low. memory addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. following this, the bus master sends the device select code, shown in table 2 (on serial data (sda), most significant bit first). the device select code consists of a 4-bit device type identifier, and a 2-bit chip enable ?address? (e1, e2). to address the memory array, the 4-bit device type identifier is 1010b. up to four memory devices can be connected on a single i 2 c bus. each one is given a unique 2-bit code on the chip enable (e1, e2) inputs. when the device select code is received on serial data (sda), the device only responds if the chip enable address is the same as the value on the chip en- able (e1, e2) inputs. the 8 th bit is the read/write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, it deselects itself from the bus, and goes into stand- by mode. table 2. device select code 1 note: 1. the most significant bit, b7, is sent first. device type identifier chip enable address rw b7 b6 b5 b4 b3 b2 b1 b0 device select code 1 0 1 0 e2 e1 a16 rw
7/21 m24m01 figure 5. i 2 c bus protocol table 3. operating modes note: 1. x = v ih or v il . mode rw bit wc 1 bytes initial sequence current address read 1 x 1 start, device select, rw = 1 random address read 0x 1 start, device select, rw = 0, address 1 x restart, device select, rw = 1 sequential read 1 x 1 similar to current or random address read byte write 0 v il 1 start, device select, rw = 0 page write 0 v il 128 start, device select, rw = 0 scl sda scl sda sda start condition sda input sda change ai00792b stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition
m24m01 8/21 figure 6. write mode sequences with wc =1 (data write inhibited) write operations following a start condition the bus master sends a device select code with the rw bit reset to 0. the device acknowledges this, as shown in figure 7, and waits for two address bytes. the device re- sponds to each address byte with an acknowledge bit, and then waits for the data byte. writing to the memory may be inhibited if write control (wc ) is driven high. any write instruction with write control (wc ) driven high (during a pe- riod of time from the start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in figure 6. each data byte in the memory has a 17-bit ad- dress. the most significant bit, a16, is sent with the device select code, and the remaining bits, a15-a0, in the two address bytes. the most sig- nificant byte is sent first, followed by the least sig- nificant byte. bits a16 to a0 form the address of the byte in memory. when the bus master generates a stop condition immediately after the ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. after the stop condition, the delay t w , and the suc- cessful completion of a write operation, the de- vice?s internal address counter is incremented automatically, to point to the next byte address af- ter the last one that was modified. during the internal write cycle, serial data (sda) is disabled internally, and the device does not re- spond to any requests. byte write after the device select code and the address bytes, the bus master sends one data byte. if the stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01120c page write (cont'd) wc (cont'd) stop data in n ack ack ack no ack r/w ack ack ack no ack r/w no ack no ack
9/21 m24m01 addressed location is write-protected, by write control (wc ) being driven high, the device replies with noack, and the location is not modified. if, in- stead, the addressed location is not write-protect- ed, the device replies with ack. the bus master terminates the transfer by generating a stop con- dition, as shown in figure 7. page write the page write mode allows up to 128 bytes to be written in a single write cycle, provided that they are all located in the same ?row? in the memory: that is, the most significant memory address bits (b16-b7) are the same. if more bytes are sent than will fit up to t he end of the row, a condition known as ?roll-over? occurs. this should be avoided, as data starts to become overwritten in an implemen- tation dependent way. the bus master sends from 1 to 128 bytes of data, each of which is acknowledged by the device if write control (wc ) is low. if write control (wc ) is high, the contents of the addressed memory loca- tion are not modified, and each data byte is fol- lowed by a noack. after each byte is transferred, the internal byte address counter (the 7 least sig- nificant address bits only) is incremented. the transfer is terminated by the bus master generat- ing a stop condition. figure 7. write mode sequences with wc =0 (data write enabled) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01106c page write (cont'd) wc (cont'd) stop data in n ack r/w ack ack ack ack ack ack ack r/w ack ack
m24m01 10/21 figure 8. write cycle polling flowchart using ack minimizing system delays by polling on ack during the internal write cycle, the device discon- nects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. the maximum write time (t w ) is shown in table 12, but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 8, is: ? initial condition: a write cycle is in progress. ? step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). ? step 2: if the device is busy with the internal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). write cycle in progress ai01847c next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write operation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no start condition continue the write operation continue the random read operation
11/21 m24m01 figure 9. read mode sequences note: 1. the seven most significant bits of the device select code of a random read (in the 1 st and 4 th bytes) must be identical. read operations read operations are performed independently of the state of the write control (wc ) signal. after the successful completion of a read opera- tion, the device?s internal address counter is incre- mented by one, to point to the next byte address. random address read a dummy write is first performed to load the ad- dress into this address counter (as shown in fig- ure 9) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the rw bit set to 1. the device acknowledges this, and out- puts the contents of the addressed byte. the bus master must not acknowledge the byte, and termi- nates the transfer with a stop condition. current address read for the current address read operation, following a start condition, the bus master only sends a de- vice select code with the rw bit set to 1. the de- vice acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master ter- start dev sel * byte addr byte addr start dev sel data out 1 ai01105c data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr byte addr sequential random read start dev sel * data out 1 stop ack r/w no ack ack r/w ack ack ack r/w ack ack ack no ack r/w no ack ack ack ack r/w ack ack r/w ack no ack
m24m01 12/21 minates the transfer with a stop condition, as shown in figure 9, without acknowledging the byte. sequential read this operation can be used after a current ad- dress read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the de- vice continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 9. the output data comes from consecutive address- es, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. acknowledge in read mode for all read commands, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. if the bus master does not drive serial data (sda) low during this time, the device termi- nates the data transfer and switches to its stand- by mode. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh).
13/21 m24m01 maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 4. absolute maximum ratings note: 1. compliant with the ecopack ? 7191395 specifiication for lead-free soldering processes 2. not exceeding 250c for more than 30 seconds, and peaking at 260c 3. jedec std jesd22-a114a (c1=100 pf, r1=1500 ? , r2=500 ? ) symbol parameter min. max. unit t stg storage temperature ?65 150 c t lead lead temperature during soldering 1 260 2 c v io input or output range ?0.6 4.2 v v cc supply voltage ?0.3 4.2 v v esd electrostatic discharge voltage (human body model) 3 ?3000 3000 v
m24m01 14/21 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 5. operating conditions (m24m01-v) table 6. operating conditions (m24m01-s) table 7. ac measurement conditions note: 1. output hi-z is defined as the point where data out is no longer driven. figure 10. ac measurement i/o waveform table 8. capacitance note: 1. t a = 25 c, f = 400 khz 2. sampled only, not 100% tested. symbol parameter min. max. unit v cc supply voltage 2.7 3.6 v t a ambient operating temperature ?40 85 c symbol parameter min. max. unit v cc supply voltage 1.8 3.6 v t a ambient operating temperature ?40 85 c symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc v input and output timing reference voltages 0.3v cc to 0.7v cc v symbol parameter test condition min . max . unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf t ns pulse width ignored (input filter on scl and sda) 50 ns ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
15/21 m24m01 table 9. power-up timing and v th threshold note: 1. these parameters are characterized only. table 10. dc characteristics (m24m01-v) table 11. dc characteristics (m24m01-s) symbol parameter test condition 1 min. max. unit t pu time delay to read or write instruction 200 s v th threshold voltage 1.1 1.4 v symbol parameter test condition (in addition to those in table 5) min. max. unit i li input leakage current (scl, sda, e1, e2, w c ) v in = v ss or v cc 1 a i lo output leakage current 0v v out v cc, sda in hi-z 2 a i cc supply current v cc =3.6v, f c =400khz (rise/fall time < 30ns) 2ma i cc1 stand-by supply current v in = v ss or v cc , 2.7 v v cc 3.6 v 5 a v il input low voltage (e1, e2, scl, sda, wc ) ?0.45 0.3v cc v v ih input high voltage (e1, e2, scl, sda, wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 2.5 ma, 2.7 v v cc 3.6 v 0.4 v symbol parameter test condition (in addition to those in table 6) min. max. unit i li input leakage current (scl, sda, e1, e2, wc ) v in = v ss or v cc 1 a i lo output leakage current 0v v out v cc, sda in hi-z 2 a i cc supply current v cc =3.6v, f c =400khz (rise/fall time < 30ns) 2ma i cc1 stand-by supply current v in = v ss or v cc , v cc =3.6 v 5 a v il input low voltage (e1, e2, scl, sda, wc ) ?0.45 0.3v cc v v ih input high voltage (e1, e2, scl, sda, wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 2.5 ma, 2.7 v v cc 3.6 v 0.4 v r l = 2.2 k ? , 1.8 v v cc 3.6 v 0.2v cc v
m24m01 16/21 table 12. ac characteristics note: 1. for a restart condition, or following a write cycle. 2. sampled only, not 100% tested. 3. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. test conditions specified in table 7 and table 5 or table 6 symbol alt. parameter min. max. unit f c f scl clock frequency 400 khz t ch1ch2 t r clock rise time 20 300 ns t cl1cl2 t f clock fall time 20 300 ns t chcl t high clock pulse width high 600 ns t clch t low clock pulse width low 1300 ns t dh1dh2 2 t r sda rise time 20 300 ns t dl1dl2 2 t f sda fall time 20 300 ns t dxcx t su:dat data in set up time 100 ns t cldx t hd:dat data in hold time 0 ns t clqx t dh data out hold time 200 ns t clqv 3 t aa clock low to next data valid (access time) 205 900 ns t chdx 1 t su:sta start condition set up time 600 ns t dlcl t hd:sta start condition hold time 600 ns t chdh t su:sto stop condition set up time 600 ns t dhdl t buf time between stop condition and next start condition 1300 ns t w t wr write time 10 ms
17/21 m24m01 figure 11. ac waveforms scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop condition data valid tclqv tclqx tchdh stop condition tchdx start condition write cycle tw ai00795c start condition
m24m01 18/21 package mechanical figure 12. lga8 - 8 lead land grid array, package outline notes: 1. drawing is not to scale. table 13. lga8 - 8 lead land grid array, package mechanical data d e a2 a1 t1 t2 e2 e1 e3 t3 d1 lga-z01b contact 1 a ddd k symb. mm inches typ. min. max. typ. min. max. a 1.040 0.940 1.140 0.0409 0.0370 0.0449 a1 0.340 0.300 0.380 0.0134 0.0118 0.0150 a2 0.700 0.640 0.760 0.0276 0.0252 0.0299 d 8.000 7.900 8.100 0.3150 0.3110 0.3189 d1 0.100 ? ? 0.0039 ? ? e 5.000 4.900 5.100 0.1969 0.1929 0.2008 e1 1.270 ? ? 0.0500 ? ? e2 3.810 ? ? 0.1500 ? ? e3 0.390 ? ? 0.0154 ? ? k 0.100 ? ? 0.0039 ? ? t1 0.410 ? ? 0.0161 ? ? t2 0.670 ? ? 0.0264 ? ? t3 0.970 ? ? 0.0382 ? ? ddd 0.100 ? ? 0.0039 ? ?
19/21 m24m01 part numbering table 14. ordering information scheme for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales of- fice. example: m24m01 ? v la 6 t p device type m24 = i 2 c serial access eeprom device function m01 = 1 mbit (131,072 x 8) operating voltage v = v cc = 2.7 to 3.6v s = v cc = 1.8 to 3.6v package la = lga8 (land grid array) temperature range 6 = ?40 to 85 c option blank = standard packing t = tape & reel packing plating technology blank = standard snpb plating p = pb-free, rohs compliant g = green package
m24m01 20/21 revision history table 15. document revision history date rev. description of revision 02-oct-2001 1.0 lga8 package mechanical data updated datasheet released as product preview 21-jun-2002 1.1 table added on power-up timing full datasheet released 08-jan-2003 1.2 added lga maximum rating for soldering temperature 22-oct-2003 2.0 table of contents, and pb-free options added. minor wording changes in summary description, power-on reset, memory addressing, write operations, read operations. v il (min) improved to -0.45v. 23-jan-2004 3.0 i cc1 (max) changed to 5a. 23-jun-2004 4.0 product is now ?not for new design?
21/21 m24m01 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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